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© 2025 CYY

Theme Typography by Makito

Proudly published with Hexo

vhdl

发布于 2023-03-02 vhdl 

做个备份，怕打了半天，又丢了

为了方便，均为小写，quartus版本为13.1

四位频率计
3-8译码器
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library ieee;
use ieee.std_logic_1164.all;
entity decoder is
Port(aa:in std_logic_vector(2 downto 0);
	qq:out std_logic_vector(7 downto 0));
end decoder;
architecture one of decoder is
begin
	process(aa)
	begin
		case aa is
			when "000"=>qq<="00000001";
			when "001"=>qq<="00000010";
			when "010"=>qq<="00000100";
			when "011"=>qq<="00001000";
			when "100"=>qq<="00010000";
			when "101"=>qq<="00100000";
			when "110"=>qq<="01000000";
			when "111"=>qq<="10000000";
		end case;
	end process;
end one;
十进制加法计数器
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt10 is
port(clk: in std_logic;
	clr:in std_logic;
	cs:in std_logic;
	qq: buffer std_logic_vector(3 downto 0);
	co:out std_logic);
end cnt10;
architecture one of cnt10 is
begin	
	process(clk,clr,cs)
		begin
			if(clr='1')then
				qq<="0000";
			elsif(clk'event and clk='1')then
				if (cs='1')then
					if(qq=9)then
						qq<="0000";
					else
						qq<=qq+1;
					end if;
				end if;
			end if;
		end process;
	process(qq)
		begin
			if(qq=9)then
				co<='0';
			else
				co<='1';
			end if;
		end process;
end one;
锁存
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;

entity lock is
port(le : in std_logic;
	dd: in std_logic_vector(3 downto 0);
	qq: out std_logic_vector(3 downto 0));
end lock;
architecture one of lock is
begin
	process(le,dd)
		begin
			if(le='1')then
				qq<=dd;
			end if;
		end process;
end one;

译码，LED显示
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library ieee;
use ieee.std_logic_1164.all;

entity decoder is
Port(din:in std_logic_vector(3 downto 0);
	led7s:out std_logic_vector(6 downto 0));
end decoder;
architecture one of decoder is
begin
	process(din)
		begin
			case din is
				when"0000"=>led7s<="1000000";
				when"0001"=>led7s<="1111001";
				when"0010"=>led7s<="0100100";
				when"0011"=>led7s<="0110000";
				when"0100"=>led7s<="0011001";
				when"0101"=>led7s<="0010010";
				when"0110"=>led7s<="0000010";
				when"0111"=>led7s<="1111000";
				when"1000"=>led7s<="0000000";
				when"1001"=>led7s<="0010000";
				when"1010"=>led7s<="0001000";
				when"1011"=>led7s<="0000011";
				when"1100"=>led7s<="1000110";
				when"1101"=>led7s<="0100001";
				when"1110"=>led7s<="0000110";
				when"1111"=>led7s<="0001110";
				when others=>led7s<=null;
			end case;
		end process;
end;

LED存在共阴共阳问题，若显示不对，取相反即可

若仍然不对，校对引脚，还是不行的话，看着改译码信号，能亮了肯定有对应信号让它亮

四位频率计的control模块
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library ieee;
use ieee.std_logic_1164.all;

entity control is
	port(clk: in std_logic;
		cs,clr,le: out std_logic);
end control;

architecture behav of control is
signal current_state,next_state:std_logic_vector(3 downto 0);
constant st0: std_logic_vector:="0011";
constant st1: std_logic_vector:="0010";
constant st2: std_logic_vector:="0110";
constant st3: std_logic_vector:="0111";
constant st4: std_logic_vector:="0101";
constant st5: std_logic_vector:="0100";
constant st6: std_logic_vector:="1100";
constant st7: std_logic_vector:="1101";
constant st8: std_logic_vector:="1111";
constant st9: std_logic_vector:="1110";

begin
	com1:process(current_state)
		begin
			case current_state is
				when st0=>next_state<=st1;clr<='1';cs<='0';le<='0';
				when st1=>next_state<=st2;clr<='0';cs<='1';le<='0';
				when st2=>next_state<=st3;clr<='0';cs<='1';le<='0';
				when st3=>next_state<=st4;clr<='0';cs<='1';le<='0';
				when st4=>next_state<=st5;clr<='0';cs<='1';le<='0';
				when st5=>next_state<=st6;clr<='0';cs<='1';le<='0';
				when st6=>next_state<=st7;clr<='0';cs<='1';le<='0';
				when st7=>next_state<=st8;clr<='0';cs<='1';le<='0';
				when st8=>next_state<=st9;clr<='0';cs<='1';le<='0';
				when st9=>next_state<=st0;clr<='0';cs<='0';le<='1';
				when others=>next_state<=st0;clr<='0';cs<='0';le<='0';
			end case;
		end process com1;

		reg:process(clk)
			begin
				if(clk'event and clk='1')then
					current_state<=next_state;
				end if;
			end process reg;
end;

虽然在同一条里，clr，cs，le并不是同时变化的，竞争冒险
实际中，le锁存信号还为1时，clr清零信号为1，现实为绝大部分时间为0，LED只有在le那段时间显示实际数字

解决方法：加个三个都为0的状态即可

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when st0=>next_state<=st1;clr<='1';cs<='0';le<='0';
.....
when st9=>next_state<=st0;clr<='0';cs<='0';le<='1';

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© 2025 CYY

Theme Typography by Makito

Proudly published with Hexo